on Computer Design (ICCD), 2008.ġ2.lsi.4 - Abstract models for estimating energy consumption in multicores Marculescu, “Contention-aware Application Mapping for Network-on-Chip Communication Architectures,” Proc. Moraes, “Congestion-aware task mapping in heterogeneous MPSoCs,” System-on-Chip, 2008. Requirements: good background in algorithms, concurrent programmingĭesired: scheduling algorithms ( RTS / CRT) how much processing overhead is due to the mapping heuristic itself?.which sort of information about the multicore system does the mapping heuristic requires, and how much resources one needs to store and transmit such information?.when to re-map a particular task? (it could be receiving data or having data being sent to it over the network).Important points to be observed when implementing the mapping heuristics include: The goal of this work is to implement and compare dynamic mapping heuristics, so that application tasks can be assigned and/or migrated to different processors during runtime in a multicore system. 229-233.ġ2.lsi.3 - Heuristics for dynamic mapping of tasks in multicore systems Glesner, Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers. Marculescu et al, "Outstanding Research Problems in NoC Design," IEEE Trans CAD of Integrated Circuits, v. Kolodny, "What is Network-on-Chip?," ACM/SIGDA Newsletter, Vol. Requirements: strong background in computer architectures, embedded systemsĭesired: networks-on-chip ( EDI), response time analysis ( RTS) simulation models or static analysis) that can comparatively evaluate different schedules.
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